VHDL implements BCD code adder

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[VHDL] implements BCD code adder

The BCD code adder calculates the sum of two four-bit binary numbers,
It consists of 9 input terminals and 5 output terminals, and it is divided into three stages: addition, correction judgment and correction.
When the added value is 0-9, the BCD code is the same as the four-bit binary code,
When the value is 10-15, the BCD code is equal to the four-bit binary code plus "0110".

As shown in the figure:
the addition module has the same function as the four-bit full adder, which will be instantiated and used:

LIBRARY IEEE; --BCD code adder implemented by structure description
 USE  IEEE . STD_LOGIC_1164 . ALL ;
 USE  IEEE . STD_LOGIC_UNSIGNED . ALL ;
ENTITY  homework8 IS
    PORT(
    AA,BB:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    FF:OUT STD_LOGIC_VECTOR( 3 DOWNTO 0 ); --FF is the final output
    CIN:IN STD_LOGIC;
    COUT:OUT STD_LOGIC
    );
END homework8;
ARCHITECTURE yejiayu OF homework8 IS
COMPONENT homework6                     
    PORT(
    A,B:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    F:OUT STD_LOGIC_VECTOR( 3 DOWNTO 0 ); -- the output of the four-bit full adder   
    CI:IN STD_LOGIC; --Low order
    CO:OUT STD_LOGIC -- high bit
    );
END COMPONENT homework6;
                                              --Fixed discriminant transition
    SIGNAL Q1:STD_LOGIC_VECTOR( 3 DOWNTO 0 ); --Q1 takes over the output of the four-bit full adder
    SIGNAL Q2:STD_LOGIC_VECTOR( 3 DOWNTO 0 ); --Q2 is the correction summand
    SIGNAL COU1:STD_LOGIC;                    
    SIGNAL COU2:STD_LOGIC;                   
BEGIN
    U1:homework6 PORT MAP(A=>AA,B=>BB,CI=>CIN,F=>Q1,CO=>COU1);--correction judgment
    COU2<=NOT((NOT COU1)AND(NOT(Q1(3) AND Q1(2)))AND(NOT(Q1(3) AND Q1(1))));
    Q2<=( 2 =>COU2, 3 =>COU2,OTHERS => '0' ); -- 2 of the summand , 3 bits are connected to COU2, and the rest are grounded
END yejiayu;

Simulation after saving:
It can also be implemented in another way:

LIBRARY  IEEE; --The implementation of behavior description 
USE  IEEE.STD_LOGIC_1164.ALL; 
USE  IEEE.STD_LOGIC_UNSIGNED.ALL; 
ENTITY  homework9 IS 
    PORT( 
    AA,BB : IN STD_LOGIC_VECTOR(3 DOWNTO 0); 
    FF : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --FF is the final output 
    CIN : IN STD_LOGIC; 
    COUT : OUT STD_LOGIC 
    ); 
END  homework9; 
ARCHITECTURE  yejiayu OF homework9 IS 
COMPONENT  homework6                         
    PORT( 
    A,B : IN STD_LOGIC_VECTOR(3 DOWNTO 0); 
    F :
    OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --Output CI of four-bit full adder    : IN STD_LOGIC; --Low 
    CO : OUT STD_LOGIC --High 
    ); 
END  COMPONENT homework6; --Revised 
                                              judgment transition 
    SIGNAL  Q1:STD_LOGIC_VECTOR(3 DOWNTO 0); --Q1 takes over the output of the four-bit full adder 
    SIGNAL  Q2:STD_LOGIC_VECTOR(3 DOWNTO 0); --Q2 is the corrected summand 
    SIGNAL  COU1:STD_LOGIC;                    
    SIGNAL  COU2:STD_LOGIC;                   
BEGIN 
    U1 : homework6 PORT MAP(A =>AA,B=>BB,CI=>CIN,F=>Q1,CO=>COU1);--modified discriminant 
    PROCESS(AA,BB,CIN) 
        BEGIN 
        IF(COU1 = '1')THEN --and >15 when 
            Q2< = Q1+6;
        ELSIF(Q1>9)THEN                           -- and >9 when 
            COU2< = '1'; 
            Q2< = Q1-10; 
        ELSIF(Q1<10)THEN 
            COU2< = '0'; 
            Q2< = Q1; 
        END  IF; 
        FF < = Q2; --value passed to FF 
        COUT< = COU2; --value passed to COUT 
    END  PROCESS; 
END  yejiayu;

Simulation after saving:

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