# [Verilog Design] Verilog implements even, odd and arbitrary fractional frequency division

write in front

even frequency division

Verilog implementation

TestBench test files

RTL view

Simulation waveform

Odd divide

Verilog implementation

TestBench test files

RTL view

Simulation waveform

Arbitrary fractional division

Verilog implementation

TestBench test files

RTL view

Simulation waveform

# write in front

In actual project engineering, different clock frequencies are often required to work, or in some written interviews, clock frequency division will also be asked, so this article introduces several common cases of clock frequency division: even frequency division, Odd frequency division, arbitrary fractional frequency division.

# even frequency division

Even frequency division is the most common frequency division method and the simplest, only a simple counter is needed. If you want to realize the clock divided by 4, you only need the counter to count from 0 to 3, and then the output clock is counted to 1. And the clock of 3 can be flipped.

## [Verilog] implementation

```//{{EJS0}} 10ps / 1ps
//
// Engineer:
// Create Date: 2022/07/24
// Design Name:
// Module Name: tb_freq_div_even
// Encode: GBK
// Description:
//
//

module tb_freq_div_even();

reg   clk;
reg   rst;
wire  clk_out;

initial begin
clk = 'd0;
rst = 'd1;
#20
rst = 'd0;
end

always #10 clk = ~clk;

freq_div_even inst_freq_div_even (
.clk(clk),
.rst(rst),
.clk_out(clk_out)
);

endmodule```

## Simulation waveform

It can be seen that the original clock is 50Mhz, and the clock is 12.5Mhz after dividing by four, which meets the design requirements. The same is true if you are designing a divide-by-eight or even larger.

# Odd divide

Compared with the even-numbered frequency division, the odd-numbered frequency division is more complicated, not only to achieve the odd-numbered frequency division but also to have a duty cycle of 50%. Here, an additional counter is required, one counter is triggered by the rising edge of the input clock, and the other counter is triggered by the falling edge of the input clock. Trigger, and finally perform phase operation on the outputs of the two counters to obtain a clock with an odd frequency division and a duty cycle of 50%.

## Verilog implementation

```//{{EJS1}} 10ps / 1ps
//
// Engineer:
// Create Date: 2022/07/24
// Design Name:
// Module Name: tb_freq_div_odd
// Encode: GBK
// Description:
//
//

module tb_freq_div_odd();

reg   clk;
reg   rst;
wire  clk_out;

initial begin
clk = 'd0;
rst = 'd1;
#20
rst = 'd0;
end

always #10 clk = ~clk;

freq_div_odd inst_freq_div_odd (
.clk(clk),
.rst(rst),
.clk_out(clk_out)
);

endmodule```

# Arbitrary fractional division

Arbitrary fractional frequency division can be divided into half-integer fractions and non-half-integer fractional frequency divisions if the division is to be finer. Because half-integers are also decimals, the design method of arbitrary fractional frequency division is uniformly implemented here.

You can also choose to directly call the PLL phase-locked loop implementation during design. For example, to achieve a frequency division of 6.3, you can first multiply the frequency of the source clock by 10 to obtain a clock of 10 times the frequency of the source clock, and then perform frequency division by 63. A clock divided by 63 can be obtained.

In addition, you can also design and implement the frequency division result N = M + P, where M is the integer part of the fractional frequency division value, P is the fractional part of the fractional frequency division value, and the decimal can be expressed as a fraction b/a+b, such as 0.3 It can be expressed as 3/7+3, at this time b = 3, then the original formula can be expressed as N = M + b/a+b, and the general division of M can get N = M(a+b) + b/a+ b = [aM + b(M+1)]/a+b, so the binary linear equation can be listed, and the division by 6.3 can be written as the formula 63/10.

The following binary linear inequalities can be obtained:

6a + 7b = 63

a + b = 10

Solved: a = 7, b = 3

It means to do 7 times of 6 frequency division first, and then do 3 times of 7 frequency division to achieve the purpose of 6.3 frequency division.

## Verilog implementation

```//{{EJS2}} 10ps / 1ps
//
// Engineer:
// Create Date: 2022/07/24
// Design Name:
// Module Name: tb_freq_div_even
// Encode: GBK
// Description:
//
//

module tb_freq_div_even();

reg   clk;
reg   rst;
wire  clk_out;

initial begin
clk = 'd0;
rst = 'd1;
#20
rst = 'd0;
end

always #10 clk = ~clk;

freq_div_decimal inst_freq_div_decimal (
.clk(clk),
.rst(rst),
.clk_out(clk_out)
);

endmodule```

## Simulation waveform

It can be seen that the simulation waveform has been divided by 6 for 7 times, and then divided by 7 for 3 times, finally forming a clock output divided by 6.3.