[Verilog] Advanced Verilog Design
Table of contents
Synthesizable value is that the designed code can be converted into a specific circuit netlist structure. Synthesis is the process of converting the behavior-level or functional-level circuit model described in [Verilog] language into RTL-level function block or gate-level circuit netlist.
- Verilog HDL behavioral or functional circuit modeling
- RTL-level function blocks
- Logic optimization
- Optimized gate-level netlist
The first two are RTL-level synthesis, and the last two are gate-level synthesis, which are the target process area and timing constraints.
Points to Note
In designing a synthesizable design, to avoid designing non-synthesizable statements, pay attention to the following:
- Do not use initialization statements (initial); do not use descriptions with delays (such as #50); do not use looping statements with indeterminate number of loops (such as forever, while, etc.).
- Design the circuit in a synchronous manner as much as possible. Unless it is the design of the critical path, the method of describing the design with gate-level components is generally not used. It is recommended to use behavioral statements to complete the design.
- The circuits implemented by combinational logic and sequential logic are allocated to different always process blocks as much as possible. The always block process has only two states: execution state and waiting state. When a specific condition comes, or enter the execution state, the execution is completed or a stop signal is encountered, the execution is terminated and the execution is entered into the waiting state.
- Only synchronous sequential logic corresponding to one clock signal is allowed to be described in an always process. Communication and coordination between multiple always processes can be carried out through signal lines, such as using a handshake mechanism.
- Try to use the global terminal of the device as the total reset of the system, because this pin has the strongest driving ability, and the delay to all logic units is basically the same. For the same reason, try to use the global clock terminal of the device as the external clock input terminal of the system.
- In the Verilog module, the task task is usually synthesized into the form of combinational logic, and the function function is usually synthesized into an independent combinational circuit logic when it is called, so use task and function as little as possible.
Common non-synthesizable statements:
Fork-join, initial, forever, while, repeat, and assign statements are not synthesizable when the left-hand side of the equation contains the bit selection of the variable.
Pipeline Design Technology
In order to improve the running speed of the system as much as possible and ensure the fast transmission of data when the system is working, the design of the pipeline is a common design method. However, if the completion of some complex logic functions requires a long delay, it will make it difficult for the system to run at a high frequency. In this case, pipeline technology can be used, that is, by inserting flip-flops in long-delay logic function blocks, complex logic operations can be completed in steps, and the delay of each part can be reduced, so that the operating frequency of the system can be increased. However, the disadvantage of pipeline is that it increases the register logic, which consumes more internal resources of the chip. It is equivalent to exchanging resources for speed. Under the premise of resources permitting, adding pipeline operations appropriately can significantly increase the operating frequency of the system.
The following is a conceptual diagram of pipeline operation. It can be seen that although more registers are consumed, the rate has been significantly improved.
Take a simple example to illustrate the realization of an 8-bit full adder, which is implemented in a non-pipeline implementation, a two-stage pipeline implementation, and a four-stage pipeline implementation. The operating frequency can be increased by 30%!
Minimizing the device resources that are easy to use in the system is also the goal pursued when designing circuits. Resource sharing is a better solution, especially sharing some modules with more useful resources can effectively reduce the resources consumed by the entire system. .
Implemented with 2 adders and 1 MUX
module add( input sel, input [3:0] a,b,c,d, output reg [4:0] sum ); always @(*) begin if (sel) begin sum = a + b; than else begin sum = c + d; end end end module
Implemented with 1 adder and 2 MUXs
module add( input sel, input [3:0] a,b,c,d, output reg [4:0] sum ); reg [3:0] atmp,btmp; always @(*) begin if (sel) begin atmp = a; btmp = b; end else begin atmp = c; btmp = c; end sum = atmp + btmp; end endmodule
It can be seen that the above two schemes can achieve the same function, but the resources they use are different. Scheme 1 is implemented with 2 adders and 1 MUX, and scheme 2 is implemented with 1 adder and 2 MUXs. , the two adders share an adder, and the adder consumes more resources than the MUX, so the second solution saves resources. This is only a small module. If it is in a relatively large project, the resources will be relatively tight. Sharing is necessary.
Attention should be paid to the resource-saving design:
- As far as possible to share complex computing units, functions and tasks can be used to define these shared data processing modules.
- The results of synthesis can be controlled by adding parentheses, etc., to achieve resource sharing as much as possible, and to reuse the calculated results.
Blocking and non-blocking assignments
When designing circuits, use blocking and non-blocking assignment points:
- When the always block is used to describe combinational logic, both blocking assignment and non-blocking assignment can be used. It is recommended to use blocking assignment.
- When designing sequential logic circuits, try to use non-blocking assignment methods.
- Describe latches and try to use non-blocking assignments.
- If you are modeling both sequential logic and combinational logic in the same always process block, it is better to use non-blocking assignment.
- In an always block, it is best not to mix blocking assignments and non-blocking assignments; for the same variable, you cannot perform both blocking assignments and non-blocking assignments, which will cause errors during synthesis.
- You cannot assign values to the same variable in two or more always processes, which will cause conflicts and errors in synthesis.