Verilog System Verilog formatting tool recommendation and installation and configuration method in Vscode environment

I have tried several [Verilog] code formatting tools recently, but I have not found a tool that is very satisfactory before. This time I found this tool launched by Google, which supports both Verilog and System Verilog. The effect is very good , and it supports custom formatting parameters. It is also very rich, and I will make a recommendation here.

1. First install this plugin in the plugin center: SystemVerilog and Verilog Formatter

Download the corresponding version according to your operating system, and add the directory where the binary file is located to the system path after decompression .

3. Open the settings option of the plug-in, select your own operating system, and you can start using it. To use it, press alt+shift+F on the code editing page .


After the above settings, the basic functions can be realized. But by default, the formatting of various code segments is automatically inferred from the existing code, which is not in line with my usage habits. I hope that the port declarations, assignments, etc. in the code are all aligned . This can be achieved with custom parameters. For specific content, please refer to:

verible/verilog/tools/formatter at master · chipsalliance/verible · GitHub

Put the parameters I use below, which can realize alignment of most common code segments.

--column_limit=300 --indentation_spaces=2 --assignment_statement_alignment=align --named_port_alignment=align  --port_declarations_alignment=align --module_net_variable_alignment=align

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