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How to use $clog2 for bit width calculation
1. Write in front
This column is the fourth independent column opened by the author in addition to [Digital IC Hand Tear Code] [ Digital IC Written Interview Sharing] [Digital IC Tool Analysis] . Knowledge of advanced grammar features , due to the unique positioning of its own column, the author will not involve basic Verilog language such as blocking non-blocking assignment, procedure blocks, data types, etc.; at the same time, limited by the author’s limited knowledge, this column will not Regarding the related content of System Verilog, according to the relevant IEEE standards, this column will focus on Verilog-2005, that is, “IEEE Std 1364™-2005” and the related content before , and provide relevant syntax characteristics in the field of IC design. The following is an advanced block diagram of Verilog. Readers with more learning needs can search for relevant English standards for learning.
2. What is $clog2
$ clog2 This is a system function, which first appeared in the Verilog-2005 version. It is in the math functions in section 17.11.1 in IEEE. Because log2 is the logarithm of binary, this system function is used in circuit design. The calculation of the bit width reflects its own convenience. It should be noted that $clog2 here is a system function that rounds up , such as
$clog2(5) Although the real value is 2.3, after rounding up, the final output is 3
3. Advantages and Cases of $clog2
In the old IEEE verilog version, if we do not use clog2 to calculate the bit width, we may need the following function function to calculate the bit width. This function itself is well understood, that is, to detect the bit width of depth by shifting , then we need The calculated numbers are then used in the process of port definition.
function integer clog2( input integer depth ); begin if(depth == 0) clog2 = 1; else if(depth != 0) for(clog2 = 0; depth > 0;clog2 = clog2 + 1) depth = depth >> 1; end endfunction
But after the introduction of $clog2, the original function can be simplified into the following process . Obviously, by using the system function $clog2, we have greatly reduced the amount of code needed to define the port width during design.
module clog2(a,b); parameter depth = 2034; input [$clog2(depth)-1:0] a; output [$clog2(depth)-1:0]b; //details about the design endmodule
4. Additional Supplements
In ” 44586 – 13.2 Verilog $clog2 function implemented improperly ” on Xlinix’s official website , the author found that version 13.2 of Xlinix’s ISE miscalculated the clog2 system function, according to the article: “The $clog2 function returns the ceiling of the logarithm to the base e (natural logarithm) rather than the ceiling of the logarithm to the base 2.” means that version 13.2 of ISE calculates clog2 with base e instead of base 2. The official reply is that ISE 13.2 only Verilog-2001 is supported, and this problem has been fixed in ISE 14.1 , so if the reader is using an old version of the development kit or does not support Verilog-2005, there may be problems due to the use of clog2, and attention should be paid. Specific additional references are as follows.
44586 – 13.2 Verilog $clog2 function implemented improperly
5. Other math functions
$clog2 is a mathematically related system function that is quite common in circuit design. IEEE also provides us with other types of system functions . The screenshots are as follows. It can be found that these functions include logarithmic functions, exponential functions, and trigonometric functions. Functions, various types of inverse trigonometric functions, and encounter specific engineering problems, readers can also call these system functions to simplify the verification work.
Six, previous [Verilog] advanced tutorial articles
- Multidimensional arrays: Thanos snaps his fingers to understand Verilog multidimensional arrays
- clog2 system function: about the system function $clog2 that Verilog automatically calculates the bit width, these are what you have to know
- UDP User Primitives: Playing around with UDP User Primitives, this article is enough
- $monitor system function: In the last few minutes before school, understand the monitor system function in Verilog
- Generate statement: a king’s time, learn the generate statement in Verilog
- parameter constant: play with parameter and localparameter, this article is enough
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