Summary of understanding of SDRAM

  1. Physical Bank, hereinafter referred to as P-Bank
    Logical Bank, hereinafter referred to as L-Bank.
  2. address

The difference between sequential and interleave

Some specific things about SDRAM have not been studied in depth, and are for reference only:
- This table should express the impact of two parameters, Burst Length and Type, on the data address of a given starting column address Burst during actual access in SDRAM Burst mode.
- Starting Column Address refers to the address that is first accessed during actual access. According to Length, Type, if you use Burst operation, read data continuously, and then output the data address in the order in the table.
- Which Length and Type to choose depends on the SDRAM controller: 1. The protocol of the upward interface (CPU side); 2. The specific composition of SDRAM, composed of several chips, etc.
The Type of Interleave, at least one of the purposes, is to meet the situation such as 32Bit to CPU bus, 16Bitx1 SDRAM, and to get enough 32Bit data as soon as possible. For example, 4 is 8/16/32, 8 is 16/32, and 16 is 32, all of which can be supported. This is because the CPU bus does not necessarily support Byte Mask for reading data.
Of course, this kind of make-up will cause the read address sequence to be chaotic, but it is guaranteed for the data throughput rate, and the circuit is complex. . .

A potential example of Burst Length=8; Start  Col Addr= 3 ; Type =Interleave:
- CPU Cache Line Size: 16Bytes;
- The CPU accesses (reads) the byte address 0 x??? 3 , resulting in Cache Miss, which in turn requires Fill Cache Line;
- The external bus of the CPU Core is 32 Bits, and the read data does not support Byte  Mask , that is, it is always assumed that the 32 bits of data are valid; in this way, the bus can send a burst of 4 consecutive reads or 4 separate read requests.
- The SDRAM controller is connected to the external bus of the Core, but the external SDRAM is a 16 - bit chip. In order to meet the requirements of the bus, the SDRAM read data must collect enough 32 Bit data as soon as possible to complete a data transfer.
At this time, you can set Burst Length = 8 , Type = Interleave, and complete the operation with as few cycles as possible and CPU external bus delay.
The disadvantage is that the address sequence may not be monotonic, and the SDRAM controller may need to buffer several bytes internally or match the behavior of the CPU Cache controller, etc. In short, it will be complicated, but the delay is small.

  • Interleave can also be an alternate read or write of BANK . As shown in the following two timing diagrams

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Key point 1: increase from address A to end of this page, it will not stop, and then increase from the starting address of this page, and so on.
Key point 2: It will not stop until the burst stop command

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