STM32 Personal Notes – Watchdog

Some of the notes are derived from the “STM32 [Embedded] Development” public account and the STM32 development guide.


Early MCUs did not have a watchdog, which could easily cause some products to crash and fail to restart. To avoid this problem, later MCUs inherit the function of watchdog internally.

There are two kinds of watchdogs, which are used in different fields. Two kinds of watchdogs: independent watchdog and window watchdog .

independent watchdog

Known from the RCC clock tree, the LSI drives an independent watchdog. Remains active even in the event of a master clock transmission failure.

IWDG is most suitable for those occasions where the watchdog is required as a function outside the main program, can work completely independently, and requires less time precision.


Free-running down counter.

Clocked by an independent RC oscillator (can operate in standby and stop modes).

A reset is generated when the down counter value reaches 0x000 (if the watchdog is activated).

IWDG is driven by LSI RC 40kHz clock. Because it is an internal RC clock, it is not an accurate 40kHz, but a variable clock between 30kHz and 60kHz.

Under the interference of the outside world, the single-chip microcomputer system will have the phenomenon that the program runs away, resulting in an infinite loop. The watchdog circuit is to avoid this situation.

The function of the watchdog is to realize the automatic reset and restart of the processor (reset signal occurs) if it does not receive the dog feeding signal within a certain period of time (implemented by the timer counter) (indicating that the MCU has hung up).

IWDG involves three registers, the primary IWDG_KR key-value register, the secondary IWDG_PR pre-allocation register and the IWDG_RLR reload register. 

IWDG_KR key value register

Write 0xCCCC to start the watchdog operation, at this time the counter starts to count down from the reset value 0xFFF. When the counter reaches the end of 0x000, a reset signal (IWDG_RESET) will be generated. 

Whenever 0xAAAA is written, the value in IWDG_RLR is reloaded into the counter to avoid a watchdog reset.

The IWDG_PR and IWDG_RLR registers are write protected. To modify the value of these two registers, 0x5555 must be written to the IWDG_KR register first. 
Writing other values ​​to the IWDG_KR register will disrupt the sequence of operations and the registers will be reprotected. A reload operation (ie, writing 0xAAAA) also enables write protection.

IWDG_PR Prescaler Register

Sets the division factor of the watchdog clock.

IWDG_RLR reload register

Save the value reloaded to the counter.

function part

IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);            //Enable/cancel register write protection 
void  IWDG_SetPrescaler ( uint8_t IWDG_Prescaler) ;          //Set IWDG prescaler value 
void  IWDG_SetReload ( uint16_t Reload) ;                    //Set IWDG reload value 
IWDG_ReloadCounter();                                    //According to IWDG Reload the value of the reload register to reload the IWDG counter, write 0XAAAA to IWDG_KR 
IWDG_Enable();                                           //Enable IWDG, write 0XCCCC to IWDG_KR

The watchdog overflow time Tout = ((4× 2^prer) × rlr ) / 40 , in ms. prer is the prescaler value (0~7), and rlr is the reload value.

Set prer = 4, rlr = 625, then you can get Tout=64×625/40=1000ms, that is, the watchdog overflow time is 1s, as long as you write 0XAAAA to IWDG_KR once within one second , it will not cause the watchdog to reset (of course it is possible to write multiple times).
What needs to be reminded here is that the clock of the watchdog is not accurate 40Khz, so when feeding the dog, it is best not to be too late, otherwise, the watchdog reset may occur.

Note that once IWDG is enabled, it cannot be disabled! If you want to close it, you can only restart it, and you can’t open IWDG after restarting, otherwise the problem will remain, so I remind everyone here, if you don’t need IWDG, don’t open it to avoid trouble.

window watchdog

The reason why it is called a window is that the dog feeding time is within a range with upper and lower limits. You can set the upper limit time and lower limit time by setting the time register: the dog feeding time cannot be too early or too late.


A programmable down counter.

Conditions for triggering chip reset:

The down counter has not been updated for a certain period of time.

Not updated within the specified time frame.

Watchdog Reset Early Warning Interrupt — Gives the application a chance to update the down counter (feed the dog) before the chip resets.

The upper limit window of the window watchdog is the configuration register WWDG_CFG: W[6:0], and the lower limit window is fixed 0x40.

A reset occurs when the window watchdog counter is outside the upper limit window or outside the lower limit window.

The clock of the window watchdog comes from PCLK1, and its frequency is 36M in the clock configuration. Then the WWDG timeout time can be calculated by the above timeout formula.

WWDG_CR Control Register

WWDG_CR: WDGA is the 8th bit, which is the activation bit of the watchdog. This bit is set by software to start the watchdog. Note that once this bit is set, it can only be cleared after a hardware reset.

WWDG_CR: T[6:0]: Watchdog counter value.

WWDG_CFG Configuration Register

Configuration register WWDG_CFG: EWI is an early wake-up interrupt bit, that is, a period of time before the reset (T[6:0]=0X40) to remind us that we need to feed the dog, otherwise it will be reset.

Therefore, we generally use this bit to set the interrupt. When the counter value of the window watchdog is reduced to 0X40, if this bit is set and the interrupt is turned on, an interrupt will be generated. We can rewrite to WWDG_CR in the interrupt. The value of the counter to achieve the purpose of feeding the dog.
Note that after entering the interrupt, the WWDG_CR must be rewritten within the time of not more than 1 window watchdog count cycle (under the condition that the PCLK1 frequency is 36M and the WDGTB is 0, the time is 113us), otherwise, the watchdog A reset will be generated.

The configuration register WWDG_CFG: WDGTB[1:0] sets the clock division factor for the counter, determines the time range that the counter can time, and thus determines the time range of the window.

The upper limit window is set by WWDG_CFG:W[6:0], the maximum is 0x7F, which is 127. The minimum is 0x40, which is 64. So the value range is 0x40~0x7F, that is, 64~127.

WWDG_SR Status Register

Only one bit is used, WWDG_SR: EWIF. A flag used to record whether there is an early wake-up currently.

This bit is set by hardware when the counter value reaches 40h. It must be cleared by software writing 0. Writing 1 to this bit has no effect. Even if the interrupt is not enabled, this bit will be set to 1 when the value of the counter reaches 0x40.

related functions

RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE);    // WWDG clock enable 
void  WWDG_SetWindowValue ( uint8_t WindowValue );         //Set the upper window value 
void  WWDG_SetPrescaler ( uint32_t WWDG_Prescaler );       //Set the frequency division value 
WWDG_EnableIT () ;                                        //Enable window watchdog interrupt
void  WWDG_Enable ( uint8_t Counter );                     //Set the initial value of the counter and enable the window watchdog at the same time

the difference

Use condition comparison:

Feature comparison:

Same point


The difference between the two:

The independent watchdog has no interrupts, and the windowed watchdog has interrupts.

The independent watchdog is divided into hardware and software, and the window watchdog can only be controlled by software.

The independent watchdog has only a lower limit, and the windowed watchdog has a lower limit and an upper limit.

The independent watchdog is 12-bit decremented, and the windowed watchdog is 7-bit decremented.

The independent watchdog uses the internal RC oscillator of about 40kHz, and the window watchdog uses the system clock APB1.

The independent watchdog has no interrupt function, as long as the counter value is reloaded before the counter decreases to 0 (lower limit), no reset will be generated.

Be careful when the watchdog and an external reset IC exist at the same time, the external circuit may prevent the watchdog from being reset.

The window watchdog has an interrupt. The function of this interrupt is to generate an interrupt when the counter reaches the lower limit of 0x40, allowing you to feed the dog. If the dog is not fed, the system reset will be generated when the value of the counter becomes 0x3f. Even if you feed the dog, you should feed the dog quickly in the interrupt, or the counter will decrease by 1 after a long time and it will become 0x3f to reset.

The window watchdog also has an upper limit value, and the counter can only be loaded if the counter value is between the upper limit value and the lower limit value, otherwise a system reset will be generated. When the upper limit value is smaller than the lower limit value, it is meaningless.

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