[HDLBits Brush Question 2] Verilog Language (2) Vectors section

Hits: 0

Table of contents

write in front

Vectors

Vector0

Vector1

Vector2

Vectorgates

Gates4

Vector3

Vectorr

Vector4

Vector5

write in front

Coming to the vector part of [Verilog] syntax, this part is still relatively simple, so only the title, code and simulation results are given, and the rest will not be repeated.

Vectors

Vector0

Build a circuit with one 3-bit input, then output the same vector and split it into three separate 1-bit outputs. Wire the output to position 0, position 1, etc. of the input vector. In the graph, tick marks with numbers next to them represent the width of the vector (or “bus”), rather than drawing a separate line for each bit in the vector.  

module top_module ( 
    input wire [2:0] vec,
    output wire [2:0] outv,
    output wire o2,
    output wire o1,
    output wire o0  ); // Module body starts after module declaration

assign  outv = item; 
assign  o2 = vec[2]; 
assign  o1 = vec[1]; 
assign  o0 = vec[0];

endmodule

Simulation waveform

Vector1

The endianness (or “direction” as it is informally called) of the vector is the least significant bit with the lower index (little endian, e.g. [3:0]) or the higher index (big endian, e.g. [0:] 3]). In Verilog, once a vector is declared in a particular endianness, it must always be used in the same way. For example, it is illegal to write in a statement. It’s good practice to be consistent with endianness, because weird errors will occur if you allocate or use vectors with different endianness together.

Build a combinatorial circuit to split the input halfword (16 bits, [15:0]) into lower [7:0] and upper [15:8] bytes

module top_module( 
    input wire [15:0] in,
    output wire [7:0] out_hi,
    output wire [7:0] out_lo );

assign out_hi = in[15:8];
assign out_lo = in[7:0];

endmodule

Simulation waveform

Vector2

A 32-bit vector can be thought of as containing 4 bytes (bits [31:24], [23:16], etc.). Build a circuit that will reverse the endianness of a 4-byte word.

module top_module( 
    input wire [15:0] in,
    output wire [7:0] out_hi,
    output wire [7:0] out_lo );

    assign out[31:24] = in[7:0];
    assign out[23:16] = in[15:8];
    assign out[15:8] = in[23:16];
    assign out[7:0] = in[31:24];

endmodule

This operation is often used when the byte order of a piece of data needs to be swapped, such as between little-endian x86 systems and the big-endian format used in many Internet protocols.

module top_module( 
    input [2:0] a,
    input [2:0] b,
    output [2:0] out_or_bitwise,
    output out_or_logical,
    output [5:0] out_not
);

assign out_or_bitwise = a | b;
assign out_or_logical = a || b;
assign out_not[5:3] = ~b;
assign out_not[2:0] = ~a;

endmodule

Simulation waveform

Vectorgates

Build a circuit with two 3-bit inputs that compute the bitwise OR of two vectors, the logical OR of two vectors, and the negation (NOT) of two vectors. Put the inverse of , in the upper half (i.e. bits [5:3]), and put the inverse of , in the lower half.

module top_module( 
    input [3:0] in,
    output out_and,
    output out_or,
    output out_xor
);
assign out_and = ∈
assign out_or = |in;
assign out_xor = ^in;

endmodule

Simulation waveform

Gates4

Build a combinational circuit with four inputs, in [3:0].
There are 3 outputs:

  • .out_and: Output 4 input AND gates.
  • .out_or: 4 Inputs the output of the OR gate.
  • .out_xor: Output 4 input XOR gates.

module top_module (
    input [4:0] a, b, c, d, e, f,
    output [7:0] w, x, y, z );

    wire [31:0]   combine;
    assign combine = {a,b,c,d,e,f,{2'b11}};
    assign w = combine[31:24];
    assign x = combine[23:16];
    assign y = combine[15:8];
    assign z = combine[7:0];

endmodule

Waveform Simulation

Vector3

Bit concatenator
Given several input vectors, concatenates them together, and splits them into multiple output vectors.
There are six 5-bit input vectors: a, b, c, d, e, and f for a total of 30-bit inputs. There are four 8-bit output vectors: w, x, y, and z for 32-bit output. The output should be the concatenation of the input vectors followed by two 1s.

module top_module( 
    input [7:0] in,
    output [7:0] out
);

assign out = {in[0],in[1],in[2],in[3],in[4],in[5],in[6],in[7]};

endmodule

Waveform Simulation

Vectorr

Given an 8-bit input vector [7:0], reverse its bit ordering.

module top_module (
    input [7:0] in,
    output [31:0] out );

    assign out = {{24{in[7]}},in};

endmodule

Simulation waveform

Vector4

Build a circuit that signs an 8-bit number and extends it to 32 bits.
This requires concatenating 24 copies of the sign bit (ie, copying bit[7] 24 times), followed by the 8-bit number itself.  

module top_module (
    input a, b, c, d, e,
    output [24:0] out );

assign out = {{~{5{a}}^{a,b,c,d,e}},{~{5{b}}^{a,b,c,d,e}},
{~{5{c}}^{a,b,c,d,e}},{~{5{d}}^{a,b,c,d,e}},{~{5{e}}^{a,b,c,d,e}}};

endmodule

No simulation waveform

Vector5

Given five 1-bit signals (a, b, c, d, and e), compute all 25 pairwise 1-bit comparisons in the 25-bit output vector. If the two bits being compared are equal, the output should be 1. 
out[24] = ~a ^ a; // a == a, so out[24] is always 1.
out[23] = ~a ^ b;
out[22] = ~a ^ c;
 …
out [1] = ~e^d;
out[0] = ~e^e;

  • The top vector is the concatenation of 5 repetitions of each input
  • The bottom vector is the 5 repetitions of the 5 inputs concatenated

module top_module (
    input a, b, c, d, e,
    output [24:0] out );

assign out = {{~{5{a}}^{a,b,c,d,e}},{~{5{b}}^{a,b,c,d,e}},
{~{5{c}}^{a,b,c,d,e}},{~{5{d}}^{a,b,c,d,e}},{~{5{e}}^{a,b,c,d,e}}};

endmodule

No simulation waveform

You may also like...

Leave a Reply

Your email address will not be published.